1. Field of the Invention
The present invention relates to an input circuit, an output circuit, and an input/output circuit and a signal transmission system using the same input/output circuit.
2. Description of the Related Art
There are two modes for transmitting logical signals by using small-amplitude transmission signals via a transmission line such as for example a dual bus line between a plurality of integrated circuits by using a communication transmission device, a computer, etc; a single-phase transmission mode and a differential transmission mode.
The single-phase transmission mode permits a small-amplitude signal utilized in signal transmission, to be transmitted via a dual bus line, while the differential transmission mode permits a small-amplitude signal equivalent to a transfer signal for the single-phase transmission mode to be transmitted via one line of the dual bus line and, at the same time, to permit a signal obtained by converting only the phase of the above-mentioned small-amplitude signal, to be transmitted via the other line of the dual bus line. The following will describe the differential transmission mode.
When such a differential transmission mode is used to transmit logical signals using the above-mentioned two signals via a dual bus line between a plurality of integrated circuits, an output circuit is employed which sends the logical signals onto these transmission lines. In a case where this output circuit is used to transmit logical signals, a logical signal to be transmitted (also called transmission signal) represents, respectively, a logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d when one of the two transmission lines is of a high-level voltage and the other is of a low-level voltage and logical value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d when one of the dual transmission line is of a low-level voltage and the other is of a high-level voltage. When an output circuit is outputting a logical value 1 or 0, it is said to be outputting a state 1 or a state 0 respectively.
In most cases, a voltage amplitude between a high level and a low level of those two output states has been of such a value of a supply voltage fed to integrated circuits.
In recent years, however, in more and more cases an extremely small amplitude of a signal is transmitted. In a case of a CMOS interface, for example, an amplitude of its conventional transmission signal has typically been about 5V or about 3V, which is nearly equivalent to a feeding supply voltage. As against this, in a case of for example a small-amplitude of signal transmission for an LVDS (Low Voltage Differential Signaling) interface, its signal amplitude in recent years is very small value of about 0.3V.
The reason why a signal amplitude is reduced to such a small value is that the reduction has large effects in for example improving a transmission rate and decreasing power dissipation and noise which occurs during signal transmission.
Thus, there is a need to use a low-amplitude interface output circuit for sending of a low-amplitude signal, in order to obtain the above-mentioned effects in an integrated circuit which has a basic concept of high-speed performance or low-power dissipation.
A low-amplitude interface output circuit which may meet such a need commonly uses as its output amplitude a small signal amplitude smaller than a supply voltage, in order to achieve high-speed, low-power dissipation, and low-noise performance. As such a low-amplitude interface output circuit are known, besides the above-mentioned LVDS, a configuration of GTL (Gunning Transceiver Logic), CTT (Center Tapped Termination), and PECL (Pseudo Emitter Coupled Logic). In the case of a PECL configuration of these low-amplitude interfaces for example, as against about 3V or about 5V as a value of its supply voltage, about a 0.6V is used as an amplitude of a signal which is employed. As a means for transferring such a small-amplitude signal, a terminating voltage source and a terminating resistor are utilized.
FIG. 4 shows an example of a small-amplitude interface circuit having this configuration.
This type of a low-amplitude interface circuit is used in a signal transmission system which uses integrated circuits. The low-amplitude interface circuit used, as shown in FIG. 4, in this signal transmission system is provided between its bus line 2 and input/output circuits 41, 42, 43, and 44 of a plurality of semiconductor integrated circuits IC1, IC2, and IC3 respectively. The bus line 2 consists of two lines L1 and L2 and is connected via terminating resistors RL1 and RL2 to a terminating power supply VS. This terminating power supply VS has VTT as its terminating voltage value. An input/output circuit 41 consists of an output circuit 41O and an input circuit 41I, which output circuit 41O is supplied with an Enable signal EN from a CMOS internal circuit 51. The output circuit 41O, when supplied with the Enable signal EN, is set in an operative state (enabled state) and, when not supplied with it, is set in an inoperative state (disabled state) with its output being set in a high-impedance state simultaneously. Note here that a reference character IN shown in FIG. 4 indicates an input signal sent from a CMOS internal circuit 51 to a CMOS internal circuit 41O, while a reference character OUT indicates an output signal sent from the input circuit 41I to the CMOS internal circuit 51. Reference numerals IO11 and IO12 indicate respective output terminals of the input/output circuit 41, which are connected to the two lines L1 and L2 of the bus line 2.
Description of the input/output circuits 42, 43, and 44 is omitted here because they are of the same configuration as the input/output circuit 41 and provided with subscripts of 2, 3, and 4 at their reference numerals in the input and output circuits and the CMOS internal circuit.
An example of a known circuit used as these input/output circuits 41, 42, 43, and 44 is shown in FIG. 5. An input/output circuit 10 shown in FIG. 5 comprises an output circuit 12 and an input circuit 14. The input/output circuit 10 comes in the input/output circuit 41 for example. An output circuit 12 comprises: an input-signal supply circuit 16 (see FIG. 6) which inputs input signals; a reference voltage source 18; a differential amplifier stage 20; an enabled/disable-state switching circuit 22 (see FIG. 7); a differential amplifier stage 24; and an output stage 26. The input circuit 14 comprises: a differential amplifier stage 42; an output stage 44; and a buffer B1.
The input-signal supply circuit 16 consists of a buffer 30 connected to an input terminal 28, and an inverter 32.
The differential amplifier stage 20 comprises n-channel type MOSFETs N1, N2, and N3 and resistors R1 and R2. A drain of the n-channel type MOSFET N1 is connected via the resistor R1 to the voltage source VDD and its source, to the n-channel type MOSFET N3 at its drain. Also, a drain of the n-channel type MOSFET N2 is connected via the resistor R2 to the voltage source VDD and its source, to the n-channel type MOSFET N3 at its drain. Also, a source of the n-channel type MOSFET N3 is connected to the ground potential. A gate of the n-channel type MOSFET N1 is connected is connected to the input-circuit supply circuit at its signal terminal 36. A gate of the n-channel type MOSFET N2 is connected to the input-signal supply circuit 16 at its output terminal 34. A gate of the n-channel type MOSFET N3 is connected to a reference-voltage source 18 at its output terminal. The n-channel type MOSFET N3 constitutes a current source.
The resistor R1 and the n-channel type MOSFET N1 constitute one branch circuit of the differential amplifier stage 20 and the resistor R2 and the n-channel type MOSFET N2, the other branch circuit of the differential amplifier stage 20.
The enabled/disabled-state switching circuit 22 consist of an inverter 38 which has its input connected to an input terminal 39 at its output to an output terminal 40.
Also, the differential amplifier stage 24 comprises: n-channel MOSFETs N4, N5, and N6; p-channel type MOSFETs P1 and P2; and resistors R3 and R4. The p-channel type MOSFET P1 has its source connected to the voltage source VDD and its drain, to the n-channel type MOSFET N4 at its drain via the resistor R3. The n-channel type MOSFET N4 has its source connected to the n-channel type MOSFET N6 at its drain. The p-channel type MOSFET P2 has its source connected to the voltage source VDD and its drain, to the n-channel type MOSFET N5 at its drain via the resistor R4. The n-channel type MOSFET N5 has its source connected to the n-channel type MOSFET N6 at its drain. The n-channel type MOSFET N6 has its source connected to the ground potential.
The gate of the p-channel type MOSFET O1 and that of the p-channel type MOSFET P2 are connected to the enabled/disabled-state switching circuit 22 at its output terminal 40. The n-channel type MOSFET N4 has its gate connected to the differential amplifier stage 20 at its output terminal O1. The n-channel type MOSFET N5 has its gate connected to the differential amplifier stage 20 at its output terminal O2. The n-channel type MOSFET N6 has its gate connected to the reference voltage source 18 at its output terminal. The n-channel type MOSFET N6 constitutes a current source.
The output stage 26 comprises n-channel type MOSFETs N7, N8, N9, and N10. The n-channel type MOSFET N7 has its drain connected to the voltage source VDD and its source, to an output terminal 29 (e.g., IO11 in FIG. 4). The n-channel type MOSFET N7 has its gate connected to the differential amplifier stage 24 at its output terminal O3 and also to the n-channel type MOSFET N8 at its drain. The n-channel type MOSFET N8 has its source connected to the ground potential. The n-channel type MOSFET N9 has its drain connected to the voltage source VDD and its source, to the output terminal 27 (e.g., IO12 in FIG. 4). The n-channel type MOSFET N9 has its gate connected to the differential amplifier stage at its output terminal O4 and also to the n-channel type MOSFET N10 at its drain. The n-channel type MOSFET N10 has its source connected to the ground potential.
The differential amplifier stage 42 of the input circuit 14 comprises n-channel type MOSFETs N11, N12, N13 and p-channel type MOSFETs P3 and P4. The p-channel type MOSFET P3 has its source connected to the voltage source VDD and its drain connected N11 has its source connected to the n-channel type MOSFET N13 to the n-channel type MOSFET N11 at its drain. The n-channel type MOSFET at its drain. Also, the p-channel type MOSFET P4 has its source connected to the voltage source and its drain, to the n-channel type MOSFET N12 at its drain. The n-channel type MOSFET N12 has its source connected to the n-channel type MOSFET N13 at its drain. The n-channel type MOSFET N13 has its source connected to the ground potential. Also, the gate of the p-channel type MOSFET P3 and that of the p-channel type MOSFET P4 are interconnected, while the gate and the drain of the p-channel type MOSFET P4 are interconnected.
The n-channel type MOSFET N11 has its gate connected to the input/output circuit at its output terminal IOA and that of the n-channel type MOSFET N12, to the input/output circuit 10 at its output terminal IOB. The n-channel type MOSFET N13 has its gate connected to the reference voltage source at its output terminal. The n-channel type MOSFET N13 constitutes a current source. The p-channel type MOSFETs P3 and P4 constitute an active load.
The output stage 44 comprises an n-channel type MOSFET N14 and a p-channel type MOSFET P5. The p-channel type MOSFET P5 has its source connected to the voltage source VDD and its drain connected to the n-channel type MOSFET N14 at its drain. The n-channel type MOSFET N14 has its source connected to the ground potential. An interconnection point between the drain of the p-channel type MOSFET P5 and that of the n-channel type MOSFET N14 is connected via the buffer B1 to the output terminal OUT. The n-channel type MOSFET N14 has its gate connected to the reference voltage source 16 at its output. The n-channel type MOSFET N14 constitutes an active load.
The above-mentioned buffer B1 operates to restore an input voltage level to such a level (e.g., a full VDD value or a value roughly equivalent to it) that can be used at a CMOS internal circuit.
Now, operations of the input/output circuit in this configuration are described below with reference to FIGS. 4 through 8.
Here, such a case is described that a high-level of the Enable signal which sets the output circuit 12 (e.g., output circuit 41O in FIG. 4) into an enabled state is supplied to the enabled/disabled-state switching circuit 22 at its input terminal 39 and a trailing edge of an input signal is input to the input-signal supply circuit 16 at its input terminal 28 (period {circle around (1)} in FIG. 8). The high-level Enable signal sets the output circuit into an output state, i.e. enabled state.
When the above-mentioned input signal is input, the n-channel MOSFET N1 is supplied with a high-level voltage at its gate (period {circle around (1)} in FIG. 8B), the n-channel type MOSFET N2 of the differential amplifier stage 20 is supplied at its gate with a level-level voltage (period {circle around (1)} in FIG. 8-A), to put the n-channel type MOSFET N1 into a conducting state (hereinafter expressed as xe2x80x9cturned onxe2x80x9d) and the n-channel MOSFET N2 into a non-conducting state (hereinafter expressed as xe2x80x9cturned offxe2x80x9d).
Through the n-channel MOSFET N3 which constitutes a current source for the differential amplifier stage 20 is flowing a current I1 constantly irrespective of whether the transistors which constitute a branch circuit of the differential amplifier stage 20 are on or off (see I1 in FIG. 8).
Thus, a low-level voltage is output from the output terminal O1 of the differential amplifier stage 20 and a high-level voltage, from its output terminal O2.
Also, a low-level voltage from the enabled/disabled-state switching circuit 22 is applied to the p-channel type MOSFETs P1 and P2 of the differential amplifier stage 24 at their gate, thereby turning on these transistors P1 and P2.
Then, a low-level voltage from the output terminal O1 of the differential amplifier stage 20 is applied to the n-channel type MOKSFET N4 at its gate and, at the same time, a high-level voltage from its output terminal O2 is applied to the n-channel type MOSFET N5 at its gate, thereby turning the n-channel type MOSFET N4 off and turning the n-channel MOSFET N5 on.
Thus, a high-level voltage is output from the output terminal O3 of the differential amplifier stage 24 and a low-level voltage, from the output terminal O4.
Also, a low-level voltage from the enabled/disabled-state switching circuit 22 is applied to the n-channel type MOSFET N8 and N10 of the output stage 26 at their gate (period {circle around (1)} ) in FIG. 8-C), thereby turning these transistors off.
Then, a high-level voltage from the output terminal O3 of the differential amplifier stage 24 is applied to the n-channel type MOSFET N7 of the output stage at its gate and, at the same time, a low-level voltage from the output terminal O4 is applied to the n-channel type MOSFET N9 at its gate. Both of these transistors N7 and N9 are always in an on-state because they constitute a source-follower circuit, thus operating to shift a level of a signal input to their respective gates.
Therefore, a low-level signal IOA from the output stage 26 is output to one output terminal 27 (period {circle around (1)} in FIG. 8-IOA) and a high-level signal IOB from it, to the other output terminal 29 (period {circle around (1)} in FIG. 8-IOB).
Thus output low-level signal output to the output terminal 27 and a high-level signal output to the output terminal 29 are combined to represent a signal output state (e.g., a binary value xe2x80x9c0xe2x80x9d represented by the states of these signal outputs), which is transmitted to other integrated circuits via the bus line 2.
It is here assumed for example that the above-mentioned binary value xe2x80x9c0xe2x80x9d is transmitted from the input/output circuit 42 of a signal-transmission system shown in FIG. 4 to the input/output circuit 43 in an identical semiconductor circuit IC1. In this case, the output circuit 43O of the input/output circuit 43 is set in a high-impedance state by Enable signal EN supplied from the CMOS internal circuit 53. The input circuit 43I receives binary value xe2x80x9c0xe2x80x9d transmitted via the bus line 2 and outputs it to the CMOS internal circuit 53. The CMOS internal circuit 53 thus receives binary value xe2x80x9c0.xe2x80x9d
In this case, however, although the input circuits 41I and 44I of the input/output circuits 41 and 44 also receive binary value xe2x80x9c0xe2x80x9d and output it respectively, their corresponding CMOS internal circuits 51 and 54 are, at that point in time, not in an operative state for receiving binary value xe2x80x9c0xe2x80x9d from their corresponding input circuits 41I and 44I respectively, so that they only receive binary value xe2x80x9c0xe2x80x9d supplied at their input and do not process the signal, i.e. they do not recognize the binary value xe2x80x9c0.xe2x80x9d
As mentioned above, the binary value xe2x80x9c0xe2x80x9d transmitted onto the bus line 2 is input also to the input circuit 41 of the input/output circuit 41 itself which has transmitted this binary value xe2x80x9c0xe2x80x9d, i.e. to the input circuit 14 in FIG. 5.
The low-level and high-level voltages which represent, in combination, that binary value xe2x80x9c0xe2x80x9d are input to the differential amplifier stage 42. This differential amplifier 42 is always flowing through itself a current I2 (which is shown as I2 in FIG. 8).
The above-mentioned low-level voltage is applied to the n-channel type MOSFET N11 of that differential amplifier 42 at its gate and that high-level voltage is applied to the n-channel type MOSFET N12 at its gate, thus turning off the n-channel type MOSFET N11 and turning on the n-channel type MOSFET N12.
With this, a high-level voltage is applied to the p-channel type MOSFET at its gate, to reduce the conductivity of that MOKSFET PS, thus decreasing a current flowing through that MOSFET PS (period {circle around (1)} in FIG. 8-I3). Reduction in the conductivity of this MOSFET P5 causes a low-level voltage to be applied to the buffer B1. The buffer B1 then clamps thus applied low-level voltage to a low CMOS level. Then, the low-level voltage thus clamped at a CMOS level is provided to the input circuit 14 at its output terminal OUT. Therefore, there is no possibility that a through current may flow through the CMOS transistors of the CMOS internal circuit.
Likewise, also when a high-level of the input signal IN is input to the input-signal supply circuit 16 at its input terminal 28 (period {circle around (2)} in FIG. 8), two signals are transmitted onto the bus line 2 and, at the same time, a high-level voltage which corresponds to binary value xe2x80x9c1xe2x80x9d represented by the output states (a high-level state at the output terminal 27 and a low-level state at the terminal 29) (period {circle around (2)} in FIGS. IOA and IOB) of these transmitted two signals is output from the output terminal 46 of the input circuit 14 (period {circle around (2)} in FIG. 8-OUT) . This high-level voltage is also clamped at a high CMOS level. In this case also, there is no possibility that a through current may flow through the MOC transistors of the CMOS internal circuit.
If the output circuit 12 does not transmit a signal and need not do so, the Enable signal EN applied to the enabled/disabled-state switching circuit 22 at its input terminal 39 becomes low (periods {circle around (4)} and subsequent in FIG. 8), which sets the output circuit 12 into a disabled state. Then, the enabled/disabled-state switching circuit 22 generates a high-level voltage (periods {circle around (4)} and subsequent in FIG. 8-C), to turn off the p-channel type MOSFETs P1 and P2 and turn on the n-channel type MOSFETs N8 and N10 and turns off the n-channel type MOSFETs N7 and N9 of the differential amplifier 24 of the output circuit 12, thus rendering the output circuit 12 disabled (inoperative state). At this point in time, the n-channel type MOSFETs N7 and N9 are in an off-state, so that there is provided a high-impedance state between the output terminals 27 and 29 (periods {circle around (4)} Hz and subsequent in FIGS. IOA and IOB).
Therefore, the above-mentioned conventional output circuit 12 of the input/output circuit 10 is provided with a means which puts the circuit 12 in a disabled state for saving power dissipation.
Thus the Enable signal EN operates to provide a low-level output voltage, to turn off the n-channel type MOSFETs N7 and N9, thus giving a high-impedance state of the output.
Note here that the output terminals 27 and 29 in the above-mentioned high-impedance state take on a voltage level VTT of the terminating power supply. This voltage level VTT is present at a middle between a high and low levels of the signal represented by FIGS. IOA and IOB (period {circle around (4)} in FIGS. 8-IOA and 8-IOB). The periods {circle around (5)} and subsequent in FIGS. 8-IOA and 8-IOB indicate that an input signal is supplied from a semiconductor integrated circuit in question itself or any other via the bus line 2 to the output terminals 27 and 29, which are input terminals as viewed from the input circuit 14.
If, therefore, an input signal is input via the bus line 2 from a semiconductor integrated circuit in question or any other with the output terminals 27 and 29 of the output circuit 12 in a high-impedance state, these output terminals 27 and 29 take on a voltage level of that input signal (periods {circle around (5)} and subsequent in FIG. 8).
A main purpose of the output circuit 12 of the above-mentioned conventional input/output circuit 10 is to provide a low level of the Enable signal EN in order to turn off the p-channel type MOSFETs P1 and P2 as well as the n-channel type MOSFETs N7 and N9, thus putting the output terminal in a high-impedance state.
When a high-impedance state is thus obtained, the differential amplifier stage 24 of the output circuit 12 dissipates no power for sure; nevertheless, the power dissipation as a whole cannot be eliminated because a current id always flowing the differential amplifier stage 24.
Therefore, although power is saved to some extent at the output circuit 12, it is not enough.
When the input circuit 14 is viewed from the point of power saving, as mentioned above, that circuit 14 is provided with no power saving means because its differential amplifier stage and output stage are always electrified.
Therefore, the conventional input/output circuits still have problems to solve.
Also, Japanese Laid-Open Patent Publication Sho-60-143498 only shows a circuit to interrupt the sending of output signals and tells nothing about power saving on the circuit by interrupting of the sending of that output signal.
Also, when the output circuit 12 of the input/output circuit 10 is operating, the conventional input circuit 14 outputs at its output terminal a voltage level which corresponds to binary-value signals transmitted via the bus line 2 from that output circuit 12.
With this, when the output circuit 12 is sending a signal, generally, the CMOS internal circuit connected to that output circuit 14 does not process the coming signal and does not recognize it. Therefore, when the CMOS internal circuit starts to operate, a signal desired to be received from the input circuit, i.e. a signal of an expected value is in not all cases output from the input circuit 14.
With this, even when the input circuit 14 is outputting an expected-value signal, as far as the same signal as that expected-value one is input from a semiconductor integrated circuit in question or any other, there is provided no possibility of the CMOS internal circuit receiving error data; however, if signal different from that output by the input circuit 14 is input from a semiconductor integrated circuit in question or any other, it may receive error data, which may constitute a disadvantage.
In view of the above, it is a first object of the present invention to provide an input circuit, an output circuit, an input/output circuit, and a signal transmission system provided with the same input/output circuit that can save on power dissipation by utilizing a control signal to set an output terminal in a high-impedance state.
It is a second object of the present invention to provide an input circuit, an output circuit, an input/output circuit, and a signal transmission system that can output from the input circuit a signal of an expected value which is given based on a control signal which sets an output terminal in a high-impedance state.
According to a first aspect of the present invention, there is provided an input circuit having a current source, wherein when a signal which gives rise to an input operation is not supplied, the current source for feeding power to the input circuit is stopped based on a fact that the signal is not supplied.
Also, according to a second aspect of the present invention, there is provided an output circuit having a current source, wherein when a signal which gives rise to an output operation is not supplied, the current source for feeding power to the output circuit is stopped based on a fact that the signal is not supplied.
Further, according to a third aspect of the present invention, there is provided an input/output circuit which comprises an output circuit and an input circuit which has an input terminal thereof connected with the output circuit at an output terminal thereof in such a configuration that when a control signal is supplied to the output circuit, the output terminal of the output circuit is put into a high-impedance state, wherein
such a power-feeding control circuit is provided to the input circuit that feeds power to the input circuit when the control signal is supplied and stops a current source for feeding power to the input circuit when the control signal is not supplied.
In the foregoing third aspect, a preferable mode is one wherein the control signal is supplied from one signal terminal to the input circuit and the output circuit.
Also, a preferable mode is one wherein the power-feeding control circuit provided to the input circuit acts to turn on/off a current source of a differential amplifier stage which constitutes the input circuit.
Also, a preferable mode is one wherein the power-feeding control circuit provided to the input circuit acts to turn on/off an active load of an output stage which constitutes the input circuit.
Also, a preferable mode is one wherein such a power-feeding control circuit is provided to the output circuit that feeds power to the output circuit when the control signal is not supplied to the the output circuit and stops a current source for feeding power to the output circuit when the control signal is supplied to the output circuit.
Also, a preferable mode is one wherein the output circuit is comprised of a differential amplifier stage including the current source; and a power-feeding control circuit provided to the output circuit turns on/off the current source included in the differential amplifier stage.
Also, a preferable mode is one wherein a signal output circuit which outputs a signal of an expected value based on the control signal is provided to the input circuit, to output a signal of an expected value from the signal output circuit to an output terminal of the input circuit based on the control signal supplied thereto.
According to a fourth aspect of the present, there is provided a signal transmission system which comprises an input/output circuit which circuit has: a semiconductor integrated circuit which has at least an input/output circuit which has an output circuit and an input circuit which has an input terminal thereof connected to the output circuit at an output terminal thereof in such a configuration that when a control signal is supplied to the output circuit, the output circuit has an output terminal thereof put into a high-impedance state; and a bus line which interconnects an output terminal of the output circuit of the semiconductor integrated circuit and an input terminal of the input circuit, wherein
the input circuit is provided with such a power-feeding control circuit for feeding power to the input circuit when the control signal is supplied to the input circuit and stops a current source for feeding power to the input circuit when the control signal is not supplied to the input circuit.
In the foregoing fourth aspect, a preferable mode is one wherein the output circuit is provided with such a power-feeding control circuit that feeds power to the output circuit when the control signal is not supplied to the output circuit and stops a current source for feeding power to the output circuit when the control signal is supplied to the output.
Also, a preferable mode is one wherein the control signal is supplied from one signal terminal to the input circuit and the output circuit.
Also, a preferable mode is one wherein a signal output circuit for outputting a signal of an expected value based on the control signal is provided to the input circuit, to output from the signal output circuit to the input circuit at an output terminal thereof the signal of an expected value based on the control signal supplied thereto.
Further, a preferable mode is one wherein the input circuit is comprised of a differential amplifier stage which includes the current source; and a power-feeding control circuit provided to the input circuit turns on/off the current source included in the differential amplifier stage.
Furthermore, a preferable mode is one wherein a power-feeding control circuit provided to the input circuit turns on/off an active load of an output stage which constitutes the input circuit.
Still furthermore, a preferable mode is one wherein the output circuit is comprised of a differential amplifier stage which includes the current source; and a power-feeding control circuit provided to the output circuit turns on/off the current source included in the differential amplifier stage.